1. Field of the Invention
The present invention relates to an ameliorated compound carrier board structure of Flip-Chip Chip-Scale Package that has the insulating layer between the carrier board and the substrate in the prior art replaced by an anisotropic conductive film or materials with similar structure. The anisotropic conductive film has conductive particles therein to replace the plurality of conductive openings manufactured on the insulating layer in the prior art so as to avoid the inaccuracies of distance and size of the conductive openings and the inaccuracy of the contact between the second electrode pads and the second electrical contact pads operated manually.
2. Description of the Related Art
The structure of a Flip-Chip Chip-Scale Package as shown in FIGS. 1A˜1D is from Taiwan application No. 102121661 (U.S. application Ser. No. 13/938,335) which has not been published yet. The structure is a three dimension package technology strides toward high-power, high-density, lightweight and miniaturized communication products. It can also be the main structure of Package on Package (POP) to bond with other packages or a PCB. Basically the manufacturing of the structure can be divided into two stages: carrier board stage and package stage.
FIGS. 1A and 1B are schematic diagrams before and after bonding the carrier board and the substrate which belongs to the carrier stage and has the manufacturing process as following:
a) providing a carrier board 20 on the upper surface of which a plurality of first electrical contact pads 21 and second electrical contact pads 22 are arranged as the second electrical contact pads 22 surrounding the first electrical contact pads 21, and under the bottom surface of which a plurality of third electrical contact pads 23 are arranged;
b) providing a substrate 40 having a plurality of electric conductors 41 penetrating through; the upper and lower ends of each is exposed on the top and bottom surface of the substrate 40 and is electrically connected to the bottom surface of a first electrode pad 42 and the top surface of a second electrode pad 43. The substrate 40 also has a flip region 44 with a penetrable opening for an insulating layer 30A to be pasted thereunder. The bottom surface of the second electrode pads 43 are arranged correspondingly to the top surface of the second electrical contact pads 22 for the latter to be electrically connected to the former; and the first electrical contact pads 21 is disposed in the flip region 44, bonding the insulating layer 30A with the carrier board 20 and forming the compound structure.
FIGS. 1C and 1D are schematic of a completed package manufactured by the Flip-Chip Chip-Scale package process. The process is as follows:
c) providing at least one die 50 having an active surface 51 and a non-active surface 52 arranged correspondingly; the active surface 51 has a plurality of bumps 53 contacting the first electrical contact pads 21, and a sealant material 60 is filled in the gap between the flip region 44 and the die 50 for the latter to be fixed in the flip region 44, rendering the non-active surface 52 an exposed status and providing an adhesive for a solder ball B to adhere to a third electrical contact pad 23.
With structures disclosed, when the die 50 is hot-pressed during the manufacturing process, the heat is generated in the flip region 44. The substrate 40 with low Coefficient of thermal expansion is able to withstand the thermal stress caused by the thermal conduction to avoid a thermal expansion arising from the thermal convection focused on the carrier board 20 while the substrate 40, insulating layer 30A, and compound structure are able to withstand the thermal stress. At the same time, an open area above the flip region 44 is able to accelerate the thermal convection. Thus, through the well thermal conduction and convection, the heat generated by the carrier board 20 during the process can be rapidly eliminated, solving the problem of the curving carrier board 20 due to thermal stresses; the structure therefore has the thin feature and effectiveness of mechanical enhancement, heat dissipating enhancement and less curving.
The main function of the insulating layer 30A is to insulate the bottom surface of the substrate 40 and the upper surface of the carrier board 20. However, there are still problems to be solved.
Firstly, the distance and size of the conductive openings (not shown) on the insulating layer 30A has to be manufactured by machines, increasing the prime costs and causing inaccuracies of the contact area between the substrate 40 and the carrier board 20 which may affect the insulating function when the inaccuracies are way too huge.
Secondly, when placing the insulating layer 30A, the position of the conductive openings between the second electrical contact pads 22 and the second electrode pads 43 have to be determined manually, increasing the manufacture time and possibly affect the measure of the contact area in-between. In other words, the inaccuracies of distance, size, and corresponding position of each conductive opening would result in inaccuracy of the contact area and further affect the insulating function. Therefore, there is still room for improvements.